ESD/Lu・CDM・GL test
We are accepting orders at the Kumamoto office.
ESD and Latch-Up Testing 【Applicable Standards】 ◇ JEDEC/JEITA/AEC/ESDA/MIL 【Device Specifications】 ◇ Maximum Usable Pins: 256 Pins ◇ ESD (MM・HBM): ±4000V ◇ Power Supply for LU: 4 Power Supply Specifications (each ±30V) ◇ Constant Temperature Chamber: MAX 125℃ Device Charging Model Testing 【Applicable Standards】 ◇ JEITA/EIAJ/JEDEC/EOS/AEC 【Device Specifications】 ◇ Maximum Usable Pins: 1024 Pins ◇ Applied Voltage: 0 to ±4000V (5V Steps) Gate Leakage Testing 【Applicable Standards】 ◇ AEC-Q100-006 【Test Content】 High voltage can be applied to the IC at high temperatures, testing the gate leakage of surface-mounted ICs (parasitic gate leakage due to electrical and thermal induction). An electric field is applied to the IC placed at high temperatures to investigate the occurrence of gate leakage.
- Company：レスター 厚木事業所,熊本事業所,大分事業所,鹿児島事業所
- Price：Other
